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ltc3532 1 3532fc micropower synchronous buck-boost dc/dc converter the ltc ? 3532 is a high ef? ciency, ? xed frequency, buck- boost dc/dc converter that operates from input voltages above, below or equal to the output voltage. the topology incorporated in the ic provides a continuous transfer function through all operating modes, making the product ideal for single lithium-ion, multicell alkaline or nimh ap- plications where the output voltage is within the battery voltage range. the device includes two 0.36 n-channel mosfet switches and two 0.42 p-channel switches. switching frequencies up to 2mhz are programmed with an external resistor. quiescent current is only 35a in burst mode operation, maximizing battery life in portable applica- tions. automatic burst mode operation allows the user to program the load current for burst mode operation or to control it manually. other features include a 1 a shutdown, soft-start control, thermal shutdown, and peak current limit. the ltc3532 is available in a low pro? le (0.75mm) 10-lead (3mm 3mm) dfn and 10-lead msop packages. miniature hard disk drive power supply mp3 players handheld instruments digital cameras handheld terminals single inductor regulated output with input voltages above, below or equal to the output wide v in range: 2.4v to 5.5v v out range: 2.4v to 5.25v up to 500ma peak output current synchronous recti? cation: up to 95% ef? ciency manual or programmable automatic burst mode ? operation output disconnect in shutdown programmable oscillator: 300khz to 2mhz pin compatible with ltc3440 small thermally enhanced 10-lead (3mm 3mm) dfn and 10-lead msop packages miniature hard disk drive power supply applicatio s u features descriptio u typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. sw1 v in shdn/ss burst r t sw2 v out fb v c gnd ltc3532 3532 ta01 43.2k 0.01f 200k 4.7f v in li-ion 2.5v to 4.2v 4.7h v out 3.3v 100ma to 500ma (peak) 10f 33pf 1k 340k 12.1k 220pf 200k v out 200mv/div i load 100ma/div 100s/div v in = 3v v out = 3.3v i load = 50ma to 300ma 3532 ta01b
ltc3532 2 3532fc burst, v in , v out , v c , fb ................................... ?0.3v to 6v r t ..................................................................... 0v to 5v shdn ss ss d n n n ndns n ns s s s shdn ns s n n nss s hss s s shdnss n s s s nd s s s nd shdnss n s dss dnsh nd n dsn n dd dd dn s s s s d
ltc3532 3 3532fc the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = v out = 3.6v, r t = 64.9k, unless otherwise speci? ed. electrical characteristics parameter conditions min typ max units pmos switch leakage switches a and d 0.1 10 a nmos switch on resistance switches b and c 0.36 pmos switch on resistance switches a and d 0.42 input current limit 0.8 1.1 1.45 a maximum duty cycle boost (% switch c on) buck (% switch a on) 70 100 88 % % minimum duty cycle 0% frequency accuracy 575 740 885 khz burst threshold (falling) 0.88 v burst threshold (rising) 1.12 v burst current ratio ratio of i out to i burst 8000 error amp avol 90 db error amp source current v c = 1.4v 15 a error amp sink current v c = 2v 310 a shdn /ss threshold when ic is enabled when ea is at maximum boost duty cycle 0.4 1 2.2 1.5 v v shdn /ss input current v shdn = 5.5v 0.01 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3532e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 85c operating temperature range are assured by design, characterization and correlations with statistical process controls. note 3: current measurements are performed when the outputs are not switching. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. ef? ciency and power loss vs load autoburst mode ef? ciency and power loss vs load fixed frequency and burst mode quiescent current vs v in typical perfor a ce characteristics uw t a = 25c, unless otherwise speci? ed. load current (ma) 60 efficiency (%) power loss (mw) 80 100 50 70 90 0.1 10 100 1000 3532 g01 40 1 10 1000 0.1 100 0.01 1 power loss v out = 3.3v efficiency 3v 3.6v 4.2v load current (ma) 60 efficiency (%) power loss (mw) 80 100 50 70 90 0.1 10 100 1000 3532 g02 40 1 1000 100 10 1 0.1 burst efficiency fixed frequency efficiency fixed frequency power loss burst power loss v in (v) 2.5 0 v in quiescent current (ma) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 5.5 3532 g03 v in quiescent current burst mode (a) 75 80 70 65 55 50 45 60 40 burst mode 2000khz 1000khz 500khz 1500khz not switching
ltc3532 4 3532fc temperature (c) v in = 3.6v C55 frequency (mhz) 1000 1050 1100 95 3532 g07 950 900 800 C5 45 850 1200 1150 temperature (c) C55 1.196 feedback voltage (v) 1.201 1.211 1.216 1.221 45 1.241 3532 g08 1.206 C5 95 1.226 1.231 1.236 v out 200mv/div i load 100ma/div 100s/div c out = 10f v in = 3.6v v out = 3.3v 3535 g09 ef? ciency vs frequency peak current clamp and limit vs v in automatic burst threshold vs r burst burst mode to fixed frequency transition switch pins in buck-boost mode switch pins before entering boost mode typical perfor a ce characteristics uw frequency vs temperature feedback voltage vs temperature load transient response in fixed frequency mode t a = 25c, unless otherwise speci? ed. frequency (khz) 500 80 efficiency (%) 84 86 88 90 92 94 1000 1500 3532 g04 96 98 100 82 2000 v in = 3.6v v out = 3.3v v in (v) 2.4 input current (a) 0.8 1.0 1.2 5.4 3532 g05 0.6 0.4 0 3.4 4.4 0.2 1.6 1.4 v out = 3.3v i clamp i limit burst resistor (k) 150 10 load current (ma) 20 30 40 50 60 70 250 350 450 550 3532 g06 leave burst enter burst v out = 3.3v v in = 3.6v sw1 2v/div sw2 2v/div 40ns/div v in = 3.3v v out = 3.3v i load = 100ma 3532 g11 sw1 2v/div sw2 2v/div 40ns/div v in = 2.9v v out = 3.3v i load = 100ma 3532 g12 v out 200mv/div burst pin 2v/div 400s/div c out = 22f v in = 3.6v v out = 3.3v 3532 g10
ltc3532 5 3532fc sw2 5v/div sw1 5v/div inductor current 500ma/div v out 100mv/div 4s/div v in = 4.2v v out = 3.3v i load = 20ma c out = 22f 3535 g17 sw2 5v/div sw1 5v/div inductor current 500ma/div v out 100mv/div 4s/div v in = 3.75v v out = 3.3v i load = 20ma c out = 22f 340612 g16 pi fu ctio s uuu rt (pin 1): timing resistor to program the oscillator frequency. the programming range is 300khz to 2mhz. f(khz) = 48,000 r t (k 1 ) burst (pin 2): used to set the automatic burst mode op- eration threshold. place a resistor and capacitor in parallel from this pin to ground. see the applications information section for component value selection. for manual control, ground the pin to force burst mode operation, connect to v out to force ? xed frequency mode. sw1 (pin 3): switch pin where the internal switches a and b are connected. connect inductor from sw1 to sw2. an optional schottky diode can be connected from sw1 to ground. minimize trace length to minimize emi. sw2 (pin 4): switch pin where the internal switches c and d are connected. for applications with output voltages over 4.3v, a schottky diode is required from sw2 to v out to ensure sw2 does not exhibit excess voltage. gnd (pin 5): signal and power ground for the ic. v out (pin 6): output of the synchronous recti? er. a ? lter capacitor is placed from v out to gnd. v in (pin 7): input supply pin. supplies current to the inductor through sw1 and supplies internal v cc for the ic. a ceramic bypass capacitor as close to the v in pin and gnd (pin 5) is required. switch pins before entering buck mode output ripple at 100ma load burst mode, boost typical perfor a ce characteristics uw t a = 25c, unless otherwise speci? ed. burst mode, buck-boost burst mode, buck sw1 2vdiv sw2 2vdiv 40ns/div v in = 4v vout = 3.3v i load = 100ma 3535 g13 v out 50mv/div v out 50mv/div v out 50mv/div 400ns/div v out = 3.6v i out = 100ma c out = 10f 3535 g14 v in = 2.4v v in = 3.6v v in = 4.5v sw1 5v/div sw2 5v/div inductor current 500ma/div v out 100mv/div 4s/div v in = 2.4v v out = 3.3v i load = 20ma c out = 22f 3535 g15
ltc3532 6 3532fc block diagra w pi fu ctio s uuu shdn /ss (pin 8): combined soft-start and shutdown. grounding this pin shuts down the ic. tie to >1.5v to enable the ic and >2.4v to ensure the error amp is not clamped from soft-start. for burst mode operation, this pin must be pulled up to within 0.5v of v in . an rc from the shutdown command signal to this pin will provide a soft- start function by limiting the rise time of the v c pin. fb (pin 9): feedback pin. connect resistor divider tap here. the output voltage can be adjusted from 2.4v to 5.25v. the feedback reference is typically 1.22v. set v out according to the formula: v out = 1.22v ? r1 + r2 () r2 v c (pin10): error amp output: a frequency compensa- tion network is connected from this pin to the fb pin to compensate the loop. refer to the applications information section for component value selection. exposed pad (pin11): the exposed pad (dfn package) must be soldered to pcb ground for electrical contact and rated thermal performance. C + C + C + C + C + C + C + 7 pwm logic gate drivers and anticross conduction gnd uvlo 1.1a 2.3v osc peak current limit sw a sw1 v in v cc v in v in sw2 sw d error amp 1.22v reverse amp sw b sw c 5 3 4 v out 6 fb 9 burst 2 v c 10 8 shdn /ss 1 r t 3532 bd pwm comp thermal shutdown shutdown soft-start shutdown 1.22v v ref automatic burst mode control and v c hold g m = 1/60k 1a v ref sleep ss
ltc3532 7 3532fc operatio u the ltc3532 provides high ef? ciency, low noise power for applications such as portable instrumentation, digital cameras, and mp3 players. the ltc proprietary topology allows input voltages above, below or equal to the output voltage by properly phasing the output switches. the error amp output voltage on v c determines the output duty cycle of the switches. since v c is a ? ltered signal, it provides rejection of frequencies well below the switching frequency. the low r ds(on) , low gate charge synchronous switches provide high frequency pulse width modulation control at high ef? ciency. schottky diodes across the synchronous switch d and synchronous switch b are not required, but provide a lower voltage drop during the break-before-make time (typically 15ns). schottky diodes will improve peak ef? ciency by typically 1% to 2%. high ef? ciency is achieved at light loads when burst mode operation is entered and the ics quiescent current drops to a low 35a. low noise fixed frequency operation oscillator the frequency of operation is programmed by an external resistor from r t to ground, according to the following equation: f(khz) = 48,000 r t (k 1 ) error amp the error ampli? er is a voltage mode ampli? er. the loop compensation components are con? gured around the ampli? er (from fb to v c ) to obtain stability of the converter. for improved bandwidth, an additional rc feedforward network can be placed across the upper feedback divider resistor. the voltage on shdn /ss clamps the error amp output, v c , to provide a soft-start function. internal current limit there are two different current limit circuits in the ltc3532. they have internally ? xed thresholds which vary inversely with v in . the ? rst circuit is a high speed peak current limit comparator that will shut off switch a if the current exceeds 1.1a typical. the delay to output of this ampli? er is typi- cally 50ns. a second ampli? er will begin to source current into the fb pin to drop the output voltage once the peak input current exceeds 1a typical. this method provides a closed loop means of clamping the input current. during conditions where v out is near ground, such as during a short-circuit or during startup, this threshold is cut in half providing a fold back feature. for this current limit feature to be most effective, the thevenin resistance from fb to ground should be greater than 100k. reverse current limit during ? xed frequency operation, the ltc3532 operates in forced continuous conduction mode. the reverse current limit ampli? er monitors the inductor current from the out- put through switch d. once the negative inductor current exceeds 340ma typical, the ic will shut off switch d. 4-switch control figure 1 shows a simpli? ed diagram of how the four internal switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the ltc3532 as a function of the internal control voltage, v ci . depending on the control voltage, the ic will operate in either buck, buck/boost or boost mode. the v ci voltage is a level shifted voltage from the output of the error amp (v c ) (see figure 5). the four power switches are properly phased so the transfer between operating modes is continuous, smooth and transparent to the user. when v in approaches v out the buck/boost region is reached where the conduction time of the 4-switch region is typically 150ns. referring to figures 1 and 2, the various regions of operation will now be described. 3 sw1 4 sw2 pmos a nmos b 7 v in pmos d nmos c 3532 f01 6 v out figure 1. simpli? ed diagram of output switches
ltc3532 8 3532fc buck region (v in > v out ) switch d is always on and switch c is always off dur- ing this mode. when the internal control voltage, v ci , is above voltage v1, output a begins to switch. during the off-time of switch a, synchronous switch b turns on for the remainder of the time. switches a and b will alternate like a typical synchronous buck regulator. as the control voltage increases, the duty cycle of switch a increases until the maximum duty cycle of the converter in buck mode reaches d max_buck , given by: d max_buck = 100 C d4 sw % where d4 sw = duty cycle % of the 4-switch range. d4 sw = (150ns ? f) ? 100 % where f = operating frequency, hz. beyond this point the 4-switch, or buck/boost region is reached. buck/boost or 4-switch (v in ~ v out ) when the internal control voltage, v ci , is above voltage v2, switch pair ad remain on for duty cycle d max_buck , and the switch pair ac begins to phase in. as switch pair ac phases in, switch pair bd phases out accordingly. when the v ci voltage reaches the edge of the buck/boost range, at voltage v3, the ac switch pair completely phase out the bd pair, and the boost phase begins at duty cycle d4 sw . the input voltage, v in , where the 4-switch region begins is given by: operatio u 88% d max boost d min boost d max buck duty cycle 0% v4 (2.05v) v3 (1.65v) boost region buck region buck/boost region v2 (1.55v) v1 (0.9v) 3532 f02 a on, b off pwm cd switches d on, c off pwm ab switches four switch pwm internal control voltage, v ci figure 2. switch control vs internal control voltage, v ci v in = v out 1? (150ns ? f) the point at which the 4-switch region ends is given by: v in = v out (1 C d) = v out (1 C 150ns ? f) v boost region (v in < v out ) switch a is always on and switch b is always off dur- ing this mode. when the internal control voltage, v ci , is above voltage v3, switch pair cd will alternately switch to provide a boosted output voltage. this operation is like a synchronous boost regulator. the maximum duty cycle of the converter is limited to 88% typical and is reached when v ci is above v4. burst mode operation burst mode operation occurs when the ic delivers energy to the output until it is regulated and then goes into a sleep mode where the outputs are off and the ic is consuming only 35a of quiescent current from v in . in this mode the output ripple has a variable frequency component that depends upon load current, and will typically be about 2% peak-to-peak. burst mode operation ripple can be reduced slightly by using more output capacitance (47f or greater). another method of reducing burst mode operation ripple is to place a small feedforward capacitor across the upper resistor in the v out feedback divider network (as in type iii compensation). during the period where the device is delivering energy to the output, the peak switch current will be equal to 250ma typical and the inductor current will terminate at zero current for each cycle. in this mode the typical maximum average output current is given by: i out(max)burst 5 0.2 ? v in v out + v in a
ltc3532 9 3532fc 7 v in a 3 sw1 5 gnd 4 sw2 l +C 6 v out d c 250ma i inductor 0ma 3532 f03 t1 b di dt v in l operatio u figure 3. inductor charge cycle during burst mode operation 7 v in a 3 sw1 5 gnd 4 sw2 l C+ 6 v out d c 250ma i inductor 0ma 3532 f04 t2 b di dt v out l C figure 4. inductor disharge cycle during burst mode operation note that the peak ef? ciency during burst mode operation is less than the peak ef? ciency during ? xed frequency because the part enters full-time 4-switch mode (when servicing the output) with discontinuous inductor cur- rent as illustrated in figures 3 and 4. during burst mode operation, the control loop is nonlinear and cannot utilize the control voltage from the error amp to determine the control mode, therefore full-time 4-switch mode is required to maintain the buck/boost function. the ef? ciency below 1ma becomes dominated primarily by the quiescent cur- rent. the burst mode operation ef? ciency is given by: efficiency ? n?i load 35 + a + i load where n is typically 88% during burst mode operation. automatic burst mode operation control burst mode operation can be automatic or manually con- trolled with a single pin. in automatic mode, the ic will enter burst mode operation at light load and return to ? xed frequency operation at heavier loads. the load current at which the mode transition occurs is programmed using a single external resistor from the burst pin to ground, according to the following equations: enter burst mode operation: i = 10.5v r burst leave burst mode operati on: i = 7v r burst where r burst is in k and i burst is the load transition current in amps. for automatic operation, a ? lter capaci- tor should also be connected from burst to ground to prevent ripple on burst from causing the ic to oscillate in and out of burst mode operation. the equation for the minimum capacitor value is: c burst(min) * c out ?v out 60,000v where c burst(min) and c out are in f. in the event that a load transient causes the feedback pin to drop by more than 4% from the regulation value while in burst mode operation, the ic will immediately switch to ? xed frequency mode and an internal pull-up will be momentarily applied to burst, rapidly charging the burst capacitor. this prevents the ic from immediately reentering burst mode operation once the output achieves regulation. manual burst mode operation for manual control of burst mode operation, the rc net- work connected to burst can be eliminated. to force ? xed frequency mode, burst should be connected to v out . to force burst mode operation, burst should be grounded. when commanding burst mode operation manually, the circuit connected to burst should be able to sink up to 2ma. for optimum transient response with large dynamic loads, the operating mode should be controlled manually by the host. by commanding ? xed frequency operation prior to a sudden increase in load, output voltage droop can
ltc3532 10 3532fc be minimized. note that if the load current applied during forced burst mode operation (burst pin is grounded) exceeds the current that can be supplied, the output voltage will start to droop and the ic will automatically come out of burst mode operation and enter ? xed frequency mode, raising v out . once regulation is achieved, the ic will then enter burst mode operation once again, and the cycle will repeat, resulting in about 4% output ripple. note that burst mode operation is inhibited during soft-start. burst mode operation to fixed frequency transient response in burst mode operation, the compensation network is not used and v c is disconnected from the error ampli? er. during long periods of burst mode operation, leakage currents in the external components or on the pc board could cause the compensation capacitor to charge (or discharge), which could result in a large output transient when returning to ? xed frequency mode of operation, even at the same load current. to prevent this, the ltc3532 incorporates an active clamp circuit that holds the voltage on v c at an optimal voltage during burst mode operation. this minimizes any output transient when returning to ? xed frequency mode operation. for optimum transient response, type 3 compensation is also recommended to broad band the control loop and roll off past the two pole response of the output lc ? lter. (see closing the feedback loop.) soft-start the soft-start function is combined with shutdown. when the shdn /ss pin is brought above 1v typical, the ic is enabled but the ea duty cycle is clamped from v c . a de- tailed diagram of this function is shown in figure 5. the components r ss and c ss provide a slow ramping voltage on shdn /ss to provide a soft-start function. to ensure that v c is not being clamped, shdn /ss must be raised above 2.4v. to enable burst mode operation, shdn /ss must be raised to within 0.5v of v in . C + 9 10 v in error amp 1.22v 15a fb r1 r2 c p1 v c v out 8 shdn /ss c ss 1v enable signal r ss soft-start clamp to pwm comparators chip enable 3532 f05 C + v ci figure 5. soft-start circuitry operatio u
ltc3532 11 3532fc applicatio s i for atio wu u u v c fb shdn /ss v in v out r t burst sw1 sw2 gnd gnd 3532 f06 ltc3532 1 2 3 4 5 10 9 7 6 8 figure 6. recommended component placement. traces carrying high current are direct. trace area at fb and v c pins are kept low. lead length to battery should be kept short inductor selection the high frequency operation of the ltc3532 allows the use of small surface mount inductors. the inductor ripple current is typically set to 20% to 40% of the maximum inductor current. for a given ripple the inductance terms are given as follows: l boost > v in(min) ?(v out ?v in(min) ) f? 6 i l ?v out h l buck > v out ?(v in(max) ?v out ) f? 6 i l ?v in(max) h where f = operating frequency, hz il = maximum allowable inductor ripple current, a v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out(max) = maximum output load current for high ef? ciency, choose a ferrite inductor with a high frequency core material to reduce core losses. the induc- tor should have low esr (equivalent series resistance) to reduce the i2r losses, and must be able to handle the peak inductor current without saturating. molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 1a to 2a region. to minimize radiated noise, use a shielded inductor. see table 1 for a suggested list of inductor suppliers. table 1. inductor vendor information supplier web site coilcraft www.coilcraft.com murata www.murata.com sumida www.sumida.com tdk www.component.tdk.com toko www.tokoam.com output capacitor selection the bulk value of the output ? lter capacitor is set to reduce the ripple due to charge into the capacitor each cycle. the steady state ripple due to charge is given by: % ripple_boost = i out(max) ?(v out ?v in(min) )?100 c out ?v out 2 ?f % % ripple_buck = 1 8lcf 2 ? (v in(max) ?v out ) ? 100% v in(max) where c out = output ? lter capacitor in farads and f = switching frequency in hz. the output capacitance is usually many times larger than the minimum value in order to handle the transient response requirements of the converter. as a rule of thumb, the ratio of the operating frequency to the unity-gain bandwidth of the converter is the amount the output capacitance will have to increase from the above calculations in order to maintain the desired transient response. the other component of ripple is due to the esr (equiva- lent series resistance) of the output capacitor. low esr capacitors should be used to minimize output voltage ripple. for surface mount applications, taiyo yuden or tdk ceramic capacitors, avx tps series tantalum capaci- tors or sanyo poscap are recommended. see table 2 for contact information.
ltc3532 12 3532fc table 2. capacitor vendor information supplier web site avx www.avxcorp.com murata www.murata.com sanyo www.sanyovideo.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com input capacitor selection since v in is the supply voltage for the ic, as well as the input to the power stage of the converter, it is recommended to place at least a 4.7f, low esr ceramic bypass capaci- tor close to the v in and gnd pins. it is also important to minimize any stray resistance from the converter to the battery or other power source. optional schottky diodes the schottky diodes across the synchronous switches b and d are not required (v out < 4.3v), but provide a lower drop during the break-before-make time (typically 15ns) improving ef? ciency. use a surface mount schottky diode such as an mbrm120t3 or equivalent. do not use ordinary recti? er diodes, since the slow recovery times will compromise ef? ciency. for applications with an output voltage above 4.3v, a schottky diode is required from sw2 to v out . output voltage > 4.3v a schottky diode from sw2 to v out is required for output voltages over 4.3v. the diode must be located as close to the pins as possible in order to reduce the peak voltage on sw2 due to the parasitic lead and trace inductance. input voltage > 4.5v for applications with input voltages above 4.5v which could exhibit an overload or short-circuit condition, a 2/1nf series snubber is required between sw1 and gnd. a schottky diode from sw1 to v in should also be added as close to the pins as possible. for the higher input voltages, v in bypassing becomes more critical; therefore, a ceramic bypass capacitor as close to the v in and sgnd pins as possible is also required. operating frequency selection higher operating frequencies allow the use of a smaller inductor and smaller input and output ? lter capacitors, thus reducing board area and component height. how- ever, higher operating frequencies also increase the ics total quiescent current due to the gate charge of the four switches, as given by: buck: i q = (0.125 ? v in ? f) ma boost: i q = [0.06 ? (v in + v out ) ? f] ma buck/boost: i q = [f ? (0.19 ? v in + 0.06 ? v out )] ma where f = switching frequency in mhz. therefore frequency selection is a compromise between the optimal ef? ciency and the smallest solution size. closing the feedback loop the ltc3532 incorporates voltage mode pwm control. the control to output gain varies with operation region (buck, boost, buck/boost), but is usually no greater than 15. the output ? lter exhibits a double pole response, as given by: f filter ? pole = 1 2? / ?l?c out hz (in buck mode) f filter ? pole = v in 2?v out ? / ?l?c out hz (in boost mode) where l is in henrys and c out is in farads. the output ? lter zero is given by: f filter ? zero = 1 2? / ?r esr ?c out hz where r esr is the equivalent series resistance of the output capacitor. a troublesome feature in boost mode is the right-half plane zero (rhp), given by: f rhpz = v in 2 2? / ?i out ?l?v out hz applicatio s i for atio wu u u
ltc3532 13 3532fc the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network can be incorpo- rated to stabilize the loop, but at a cost of reduced band- width and slower transient response. to ensure proper phase margin using type i compensation, the loop must be crossed over a decade before the lc double pole. the unity-gain frequency of the error ampli? er with the type i compensation is given by: f ug = 1 2? / ?r1?c p1 hz referring to figure 7. most applications demand an improved transient response to allow a smaller output ? lter capacitor. to achieve a higher bandwidth, type iii compensation is required, providing two zeros to compensate for the double-pole response of the output ? lter. referring to figure 8, the location of the poles and zeros are given by: f pole1 ? 1 2? / ?32e 3 ?r1?cp1 hz (which is extremely close to dc) f zero1 = 1 2? / ?r z ?c p1 hz f zero2 = 1 2? / ?r1?c z1 hz f pole2 = 1 2? / ?r z ?c p2 hz where resistance is in ohms and capacitance is in far- ads. 1.22v r1 r2 3532 f07 fb 9 v c c p1 v out 10 C + error amp 1.22v r1 r2 3532 f08 fb 9 v c c p1 c z1 r z v out 10 c p2 C + error amp figure 7. error ampli? er with type l compensation figure 8. error ampli? er with type lll compensation applicatio s i for atio wu u u
ltc3532 14 3532fc sw1 sw1 v in shdn /ss burst r t sw2 sw2 v out fb fb vc vc gnd ltc3532 3532 ta02 shdn r4 86.6k 200k c5 4.7nf r7 200k c1 4.7f r t burst 0.01f l1 4.7h v out 3.3v 300ma c3 22f c4 150pf r9 1k r1 340k r6 12.1k c2 150pf r2 200k v in 2.7v to 4.5v sw1 sw1 v in shdn /ss burst r t sw2 sw2 v out fb fb v c v c gnd ltc3532 3532 ta03 shdn r4 28.7k c5 4.7nf r7 200k c1 4.7f r t burst l1 2.2h v out 5v 300ma c3 10f c4 68pf r9 1k r1 412k r6 12.1k c2 220pf r2 133k d1 dmbrm 110lt3 sd v in 2.5v to 4.2v three cell to 3.3v at 300ma buck-boost converter with automatic burst mode operation and soft-start li-ion to 5v boost converter with output disconnect typical applicatio s u
ltc3532 15 3532fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e)
ltc3532 16 3532fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0308 rev c ? printed in usa part number description comments ltc3440 600ma i out , 2mhz, synchronous buck- boost dc/dc converter v in : 2.5v to 5.5v, v out(range) : 2.5v to 5.5v, i q = 25a, i sd = <1a, ms10/dfn package ltc3441 1.2a i out , 1mhz, synchronous buck- boost dc/dc converter v in : 2.4v to 5.5v, v out(range) : 2.4v to 5.25v, i q = 25a, i sd = <1a, dfn package ltc3442 1.2a i out , 2mhz, synchronous buck- boost dc/dc converter v in : 2.4v to 5.5v, v out(range) : 2.4v to 5.25v, i q = 35a, i sd = <1a, dfn package LTC3443 1.2a i out , 600khz, synchronous buck- boost dc/dc converter v in : 2.4v to 5.5v, v out(range) : 2.4v to 5.25v, i q = 28a, i sd = <1a, ms10 package ltc3444 500ma i out , 1.5mhz, synchronous buck-boost dc/dc converter optimized for wcdma v in : 2.7v to 5.5v, v out(range) : 0.5v to 5.25v, i sd = <1a, 3 3 dfn package ltc3531/ ltc3531-3.3/ ltc3531-3 200ma i out , synchronous buck-boost dc/dc converters in sot-23 v in : 1.8v to 5.5v, v out(range) : 2v to 5.25v, i q = 16a, i sd = <1a, sot-23 and 3 3 dfn packages related parts sw1 sw1 v in shdn /ss burst r t sw2 sw2 v out fb fb v c v c gnd ltc3532 3532 ta04 r4 28.7k r3 200k c1 4.7f r t burst l1 2.2h v out 3.3v 300ma c3 10f c4 68pf r9 1k r1 340k r6 12.1k c2 220pf r2 200k v in 2.5v to 4.2v c5 0.01f l1: coilcraft lpo6610-222m low pro? le li-ion to 3.3v at 300ma converter with automatic burst mode operation typical applicatio u

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